Aqui está uma maneira de fazer isso em perl
:
(a versão revisada irá manipular ambas as entradas de amostra. Também parece que um ponto e vírgula dentro de []
não confunde o destaque da sintaxe de remarcação)
#! /usr/bin/perl
use strict;
sub expand {
my ($name,$start,$stop) = @_;
my $step = ( $start < $stop ? 1 : -1);
my @names=();
my $i = $start;
while ($i ne $stop + $step) {
push @names, "$name\[$i\]";
$i += $step;
}
return @names;
};
while(<>) {
chomp;
s/([(),;])/ $1/g; # add a space before any commas, semi-colons, and
# parentheses, so they get split into separate fields.
my @l=(); # array to hold the output line as it's being built
my @line = split ; # split input line into fields, with 1-or-more
# whitespace characters (spaces or tabs) between each
# field.
my $f=0; # field counter
while ($f < @line) {
if ( $line[$f] =~ m/module/io ) {
push @l,$line[$f++];
while ($f < @line) {
if ( $line[$f] =~ m/^(.*)\[(\d+):(\d+)\]$/o ) {
# expand [n:n] on module line
push @l, join(", ",expand($1,$2,$3));
} else {
push @l, $line[$f]
};
$f++;
};
} elsif ($line[$f] =~ m/^(?:input|output)$/io) {
# use sprintf() to indent first field to 10 chars wide.
$line[$f] = sprintf("%10s",$line[$f]);
push @l, $line[$f++];;
my @exp = ();
while ($f < @line) {
if ( $line[$f] =~ m/^\[(\d+):(\d+)\]$/o ) {
# extract and store [n:n] on input or output lines
@exp=($1,$2);
} elsif ( $line[$f] =~ m/^\w+$/io) {
# expand "word" with [n:n] on input or output lines
push @l,join(", ",expand($line[$f],@exp));
} else {
push @l, $line[$f];
};
$f++;
};
} else {
# just append everything else to the output @l array
push @l, $line[$f];
};
$f++;
}
print join(" ",@l),"\n";
}
Saída:
$ ./jigar.pl ./jigar.txt
module test ( temp_bus[3], temp_bus[2], temp_bus[1], temp_bus[0] , temp_B[1], temp_B[0] )
input temp_bus[3], temp_bus[2], temp_bus[1], temp_bus[0] ;
output temp_B[1], temp_B[0] ;
endmodule
Saída da sua segunda amostra:
$ ./jigar2.pl jigar2.txt
module test ( temp_bus[3], temp_bus[2], temp_bus[1], temp_bus[0] , temp_B[1], temp_B[0] , temp_C[1], temp_C[0] )
input temp_bus[3], temp_bus[2], temp_bus[1], temp_bus[0] ;
output temp_B[1], temp_B[0] , temp_c[1], temp_c[0] ;
endmodule