Fim da proteção de dados:
Handling soft errors requires many design steps. A good first step is to protect the SRAMs and DRAM with parity or EDAC. But those don’t protect flip flops in the controller’s logic circuitry, and soft errors there can also corrupt user data. One approach that Intel takes is to envelop the user data in what’s known as end-to-end data protection. When the host writes a sector, the controller appends a set of Cyclic Redundancy Check (CRC) bits (think of parity on steroids) before passing the whole bundle through the rest of the circuitry to the NAND. When the host later reads that sector, the controller checks that the CRC bits still jive with the user data. If there’s been a bit flip, the CRC will detect it. This is another aspect that can be worked out mathematically and shown to meet ultra-low silent error rate requirements.
Integridade de dados em drives de estado sólido: o que Supernovas significa para você
Portanto, é uma proteção contra pequenos erros de tempo de execução.
Aprimore a proteção de dados contra perda de energia:
During an unsafe shutdown, firmware routines in the Intel SSD 320 Series respond to power loss interrupt and make sure both user data and system data in the temporary buffers are transferred to the NAND media. Additionally, given the energy provided by the capacitor elements and urgency to recover data, firmware de-prioritizes non essential controller activities to quickly get into data saving mode ― all with no impact on overall system performance.
Proteção aprimorada de dados sobre perda de energia em a unidade de estado sólido Intel® 320 Series
Esta é a proteção de dados durante a perda de energia.